EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsCmos Circuit DesignDynamic Power ReductionIntegrated Circuit DesignMixed-signal Integrated Circuit DesignPower OptimizationVoltage ScalingAnalog Amplifier DesignAnalog Circuit DesignAuto-zeroingBandwidthCmos Analog Circuit DesignLow-power Circuit DesignRail-to-rail Input StageThreshold Voltage
Analog design in deep sub‑micron CMOS faces severe challenges, notably the low supply‑voltage constraints on switches and amplifiers. The authors discuss techniques such as low‑Vth transistors, clock boosting, switched‑OpAmp, rail‑to‑rail input stages, back‑gate driving, and CM level‑shift to mitigate these issues. The study shows that power needed for a given dynamic range and bandwidth falls with smaller feature sizes provided the signal‑swing to supply‑voltage ratio stays constant, but below 0.1 µm threshold‑voltage predictions threaten this benefit, and power estimates confirm that matching‑enhancing techniques such as Auto‑Zero and averaging are necessary.
Analog design in deep sub-micron technologies is a reality now and poses severe challenges to the circuit designer. Trends in technologies as well as circuit design are discussed. It is shown that the power required for a certain dynamic range and bandwidth decreases with minimum feature size as long as a constant ratio between signal swing and supply voltage can be maintained. Below 0.1µm channel-length, predictions of the threshold voltage endanger that requirement however. At circuit level, the problem that a low supply voltage poses on the use of switches and amplifiers is discussed. Various techniques are discussed to overcome these problems, like the use of low V th transistors, clock boosting, switched OpAmp technique, rail-to-rail input stages, back-gate driving circuits and CM level-shift techniques. Based on power estimates, the necessity of matching enhancing techniques like Auto-Zero techniques and Averaging is shown.
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