Study of Local Trapping and STI Edge Effects on Charge-Trapping NAND Flash

Abstract

Unlike the floating gate Flash device, charge-trapping (CT) devices store charges locally and are thus profoundly affected by non-uniform injection effect. The characteristics of a CT device are dominated by the local minimum-Vt region along the channel width. We have analyzed various STI structures including raised-STI, recessed-STI, and near-planar structures, and found that the program/erase characteristics are strongly impacted by the STI corner geometry due to local field enhancement (FE) and non-uniform injection effects. Moreover, both gm and S.S. vary during program/erase and thus increase programming/erasing complexity. The read disturb, program disturb, and retention characteristics are examined in detail. These conclusions apply to all CT devices.