An all-digital 50% duty-cycle corrector

Abstract

A new 50% duty-cycle corrector (DCC), designed with a purely digital technique, is presented in this paper. The novel features of the proposed DCC includes a higher reliability due to the use of the all-digital technique, a larger operating frequency range, a wider acceptable duty-cycle range for the input clock, and a faster duty-cycle correction speed, compared to conventional DCC's. The output clock has a fixed rising edge, which makes the new DCC more easily to cooperate with a delay locked loop because the locked phase will not be affected by the operation of duty-cycle correction. When designed with a 0.25-/spl mu/m CMOS technology, the acceptable duty-cycle of the input signal ranges from 2% to 98% when the clock frequency is 400 MHz and the correction operation spends only 1.5 clock cycles with the corrected duty-cycle varying from 48.8% to 52.2%.