2003 · 264 citations · 8 references
Lossy CompressionEngineeringComputer ArchitectureHardware SecurityTest Data CompressionStatistical CodingParallel ComputingLossless CompressionVariable-length CodeComputer EngineeringBuilt-in Self-testInverse ProblemsComputer ScienceData CompressionSignal ProcessingDesign For TestingEntropyProgram AnalysisSoftware TestingCompression/decompression SchemeScan Vector Compression/decompression
The paper proposes a statistical coding scheme to compress test data for core‑based designs, reducing storage and transfer requirements. The method stores vendor‑provided test vectors in compressed form in tester memory, transfers them to the chip, and uses a carefully chosen statistical code decoded by a small pipelined decoder at the core’s scan chain input. Experiments show the scheme achieves compression close to optimal Huffman coding and cuts both test storage and test time by roughly half.
A compression/decompression scheme based on statistical coding is presented for reducing the amount of test data that must be stored on a tester and transferred to each core in a core-based design. The test vectors provided by the core vendor are stored in compressed form in the tester memory and transferred to the chip where they are decompressed and applied to the core. Given the set of test vectors for a core, a statistical code is carefully selected so that it satisfies certain properties. These properties guarantee that it can be decoded by a simple pipelined decoder (placed at the serial input of the core's scan chain) which requires very small area. Results indicate that the proposed scheme can use a simple decoder to provide test data compression near that of an optimal Huffman code. The compression results in a two-fold advantage since both test storage and test time are reduced.
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Test requirements for embedded core-based systems and IEEE P1500
Y. Zorian · 2002 · 145 citations
R. Chandramouli, S. Pateras · IEEE Spectrum · 1996 · 112 citations