Selection of potentially testable path delay faults for test generation

Abstract

We present a method of path selection and test generation for path delay faults. The proposed method addresses the fact that logic circuits typically have very large numbers of paths, and a large percentage of these paths are typically untestable. The proposed method selects a set of potentially testable long paths by utilizing non-enumerative identification of untestable paths and removing untestable paths from consideration. Test generation is also applied as part of the proposed method. We demonstrate the effectiveness of the method by presenting results for benchmark circuits.