Scaling 2-layer RRAM cross-point array towards 10 nm node: A device-circuit co-design

Abstract

The resistive random access memory (RRAM) technology is a promising candidate for the replacement of NAND FLASH at ultra-scaled nodes. In this work, the scalability of a 2-layer RRAM cross-point array architecture is explored towards the 10 nm node. Device-circuit co-design methodologies are employed to optimize the array architecture. The impact of sneak paths, IR drop along the wire interconnect and RRAM device characteristics are investigated by HSPICE simulations and the memory array organization and partition are optimized by NVSim simulations. It is found that increasing the I-V nonlinearity of a memory cell by adding a cell selector helps maintain the write voltage margin at scaled nodes. With the scaling, the maximum sub-array size decreases due to the IR drop constraint thus the memory architecture evolves to a finer granularity. At the 10 nm node, by hiding a portion of the peripheral circuitry underneath the memory array, a 2-layer RRAM bank is projected to achieve ultra-high density ~3.43 Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and can enable fast write bandwith ~ 300 MB/s and read bandwidth ~1 GB/s.