2001 · 26 citations · 6 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSystem-on-chip DesignCmos Circuit DesignCurrent-voltage CharacteristicsDevice CharacterizationIntegrated Circuit DesignVery-large-scale Integration LayoutBicmos TechnologyDischarge Path DesignElectromigration-aware LayoutElectrostatic DischargeIc Physical Design VerificationLayout Parasitics ModelingParasitic ExtractionSige Bicmos Design
This work describes an ESD path verification methodology based on layout parasitic extraction. This approach was implemented in Cadence DFII. It provides information about the preferred ESD path between two pads and estimates the peak pad to pad voltage. The path can also be overlaid on the layout view. The methodology was applied to a 0.5 um BiCMOS design to improve its ESD robustness. In that case, weak ESD paths overlooked during conventional design reviews were identified and corrected. The ESD robustness improved from 1.0 kV to 2.5 kV and 100 V to 250 V for HBM and MM respectively.
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A note on two problems in connexion with graphs
E. Dijkstra · Numerische Mathematik · 1959 · 23.8K citations
An automated tool for detecting ESD design errors
S. Siha, H. Swaminathan, G. Kadamati et al. · 2002 · 41 citations
Engineering, Computer Engineering, Electrical Engineering +12