Merged CMOS/bipolar current switch logic

Abstract

Merged CMOS/bipolar logic (MCSL) is introduced and applied to a BiCMOS ripple adder. the adder shows bipolar performance without additional circuits for level conversion at the input. In contrast to a pure bipolar solution, the area and power are reduced by 50% for each bit. The advantage in area results from the smaller number of transistors and the smaller spacing of the MOS part. Only 28 transistors in comparison to 48 transistors, considering the emitter-follower and level shifter, are necessary for each bit. The advantage in power results from the smaller number of current paths. Only two gate and four emitter-follower currents rather than four gate and eight emitter-follower currents are necessary. Comparison to a pure CMOS adder cell shows a speed improvement by a factor of 5 with only a threefold increase in area.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>