A 1000 MIPS BiCMOS microprocessor with superscalar architecture

Abstract

A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe circuit techniques of the cache, TLB, register, file, and ALU (arithmetic and logic unit) operating at 250 MHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>