A 65MHz Floating-point Coprocessor For A RISC Processor

Abstract

The coprocessor contains the following hardware: an ALU functional unit, a multiplier functional unit (MPY) which also executes divides and square roots, a register file with 32 64b entries, a set of 10 instruction registers, and a gate array containing control logic. (Figure 1) All internal data busses arc 64b wide. The coprocessor is fabricated in a O.Sµm CMOS process and is packaged in a 207-pin ceramic PGA.1 The chip is 502x520mils and contains 640k transistors. Power consumption is 2.3W at 65MHz.