EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignDelay ModelingDevice ScalingInterconnect TechnologySignal IntegrityTiming AnalysisTiming ModelingBandwidthBit Error RateInterconnect ModelingInterposer TechnologySiliconThrough-silicon ViasTimingTiming Jitter
Silicon interposers and through silicon vias are new technologies that are currently being readied for production. This research examines the electrical and timing models to predict how fast this technology will scale. We show that the metrics first introduced by W.C. Elmore to the delay and bandwidth calculations of cascaded low pass elements provide excellent predictions for the interconnect signal integrity. By applying a simple transmit equalizer we show that 6 mm links will scale to over 6 Gb/s. To support the scaling calculations we review the timing jitter model that is used to calculate the timing budget at the receiver to achieve a 0 bit error rate. This technology requires such a detailed model because the geometry is too small to allow direct measurements, it must be guaranteed by design and confirmed by margin testing.
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