A DPA-resistant self-timed three-phase dual-rail pre-charge logic family

Abstract

Differential power analysis (DPA) has been shown to be a highly effective and easy to mount side-channel attack. One effective method of increasing DPA resistance is to use three-phase dual-rail pre-charge logic (TDPL), but this type of logic is vulnerable to manipulation of the clock generation/distribution hardware. If an attacker can slow down the clock, separate the evaluate phase from the discharge phase, or eliminate the discharge phase entirely, the DPA resistance of TDPL is no better than a basic dynamic dual rail logic family. To counter such attacks, we propose a self-timed three-phase dual-rail pre-charge logic family (ST-TDPL), which internally generates the discharge clock in a distributed manner. Thus, an attacker cannot split the discharge phase from the evaluate phase. We compare the area, energy, and normalized energy deviation (NED) of ST-TDPL against Simple TDPL, Simple TDPL with no discharge phase, and static CMOS using an iso-performance design point (i.e., all gates have the same delay) in an industrial 65nm bulk CMOS. The results show that ST-TDPL achieves a similarly low NED value as TDPL, while also providing protection against attacks on the clocking infrastructure.