CERN Document Server (European Organization for Nuclear Research) · 2009 · 22 citations · 8 references
EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDevice ScalingIntegrated Circuit DesignLeakage Power ReductionVoltage ScalingAnalog Circuit DesignCmos Analog Circuit DesignCmos Analog Integrated CircuitsCmos ScalingComplementary Metal-oxide-semiconductor ScalingGate Oxide ScalingLow-power Circuit DesignPower Consumption
In this paper an overview on the main issues in analog IC design in scaled CMOS technology is presented. Decreasing the length of MOS channel and the gate oxide has led to undoubted advantages in terms of chip area, speed and power consumption (mainly exploited in the digital parts). Besides, some drawbacks are introduced in term of power leakage and reliability. Moreover, the scaled technology lower supply voltage requirement has led analog designers to find new circuital solution to guarantee the required performance.
8
NMOS drive current reduction caused by transistor layout and trench isolation induced stress