NMOS drive current reduction caused by transistor layout and trench isolation induced stress

Abstract

This paper describes a previously unreported phenomenon wherein NMOS transistors of identical gate length exhibit a significant sensitivity to layout. Drive current may be reduced up to 13%, depending on diffusion overlap of gate. Mobility reduction, induced by stress from the trench isolation edge, is the root cause of the performance degradation. PMOS devices are not affected. Simulation results show that stress varies strongly with distance from the trench edge, and with overall diffusion size. Stress is also a major component of narrow-width effects, and explains why Idsat scaling with W differs for NMOS and PMOS devices.