Verilog Syntax

Verilog Syntax is the formal grammar of the Verilog hardware description language that specifies the admissible lexical tokens and their valid structural compositions in source code, typically defined in Backus–Naur Form and used to determine which sequences of symbols constitute well-formed Verilog designs.

28

Publications

1.4K

Citations

58

Authors

21

Institutions

Publications per year

2017–2026

4

Authors

58

  1. AY
    Amir Yazdanbakhsh

    Georgia Institute of Technology, United States

    3 publications · 100 citations

    3

    h-index

  2. RK
    Ramesh Karri

    New York University, United States

    3 publications · 343 citations

    3

    h-index

  3. BD
    Brendan Dolan-Gavitt

    New York University, United States

    3 publications · 343 citations

    3

    h-index

  4. BT
    Bradley Thwaites

    Georgia Institute of Technology, United States

    3 publications · 100 citations

    3

    h-index

  5. KB
    Kia Bazargan

    University of Minnesota, United States

    3 publications · 100 citations

    3

    h-index

1–5 of 58

Venues

  1. Microelectronics Journal

    2 publications · 139 citations

    2

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  2. OAR@UM (University of Malta)

    Repository · 1 publications · 10 citations

    1

    h-index

  3. Research Explorer (The University of Manchester)

    Repository · 1 publications · 12 citations

    1

    h-index

  4. 33rd Design Automation Conference Proceedings, 1996

    Conference · 1 publications · 11 citations

    1

    h-index

  5. IEEE Transactions on Industry Applications

    1 publications · 20 citations

    1

    h-index

1–5