A Conditional Statement is a control flow construct in Verilog Syntax that belongs to the class of procedural statements and is distinguished by its execution of specified blocks of code based on the evaluation of a Boolean expression at simulation time.
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48
Conditional Assertions and “Biscuit” Conditionals
Keith DeRose, Richard E. Grandy · Noûs · 1999 · 233 citations
If P, then Q: conditionals and the foundations of reasoning
Choice Reviews Online · 1990 · 138 citations
Humanities, History, Philosophy +13
1–5 of 48
Authors
97
- JS
4
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2
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2
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2
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- EME. Mukhin
Indiana University – Purdue University Indianapolis, United States
2 publications · 97 citations
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69
University of Plymouth
Plymouth, United Kingdom
4 h-index
8 publications
631 citations
Centre National de la Recherche Scientifique
Paris, France
3 h-index
4 publications
480 citations
University of North Carolina at Chapel Hill
Chapel Hill, United States
2 h-index
2 publications
97 citations
Microsoft (United States)
Redmond, United States
2 h-index
4 publications
165 citations
University of Sheffield
Sheffield, United Kingdom
2 h-index
4 publications
299 citations
Durham University
Durham, United Kingdom
2 h-index
2 publications
135 citations
The University of Queensland
Brisbane, Australia
2 h-index
3 publications
43 citations
University of California, Davis
Davis, United States
2 h-index
2 publications
99 citations
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Venues
- Thinking & Reasoning
4 publications · 117 citations
4
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- International Journal of Man-Machine Studies
3 publications · 92 citations
3
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- Annals of Mathematics
2 publications · 108 citations
2
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- Quarterly Journal of Experimental Psychology
QJEP · 2 publications · 135 citations
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- British Journal of Psychology
2 publications · 214 citations
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