Function Declaration

A Function Declaration is a syntactic construct in Verilog that specifies the name, return type, input arguments, and body of a reusable computational unit confined within a module, distinguished from procedural blocks by its inability to contain timing or blocking statements and by its purpose of computing and returning a single value.

27

Publications

1.2K

Citations

47

Authors

25

Institutions

Publications per year

2017–2026

0

Authors

47

  1. BC
    Brad Cossette

    University of Calgary, Canada

    2 publications · 62 citations

    2

    h-index

  2. KE
    Kenneth E. Iverson

    IBM Research - Thomas J. Watson Research Center, United States

    2 publications · 35 citations

    2

    h-index

  3. RJ
    Robert J. Walker

    University of Calgary, Canada

    2 publications · 62 citations

    2

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  4. PK
    Puneet Kapur

    University of Alabama at Birmingham, United States

    2 publications · 62 citations

    2

    h-index

  5. RR
    Richard Rasala

    Northeastern University, United States

    2 publications · 22 citations

    2

    h-index

1–5 of 47

Venues

  1. ACM SIGAPL APL Quote Quad

    QQ · 3 publications · 52 citations

    3

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  2. ACM SIGSAM Bulletin

    2 publications · 85 citations

    2

    h-index

  3. ACM SIGPLAN Notices

    2 publications · 31 citations

    2

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  4. 1

    h-index

  5. Gene

    1 publications · 35 citations

    1

    h-index

1–5