Subthreshold Logic Gates

Subthreshold Logic Gates is a class of digital logic circuits that operate with transistors biased in the subthreshold region, distinguishing them by enabling ultra-low-power computation through the exploitation of exponential current-voltage characteristics below the transistor threshold voltage.

36

Publications

1.5K

Citations

110

Authors

46

Institutions

Publications per year

2017–2026

3

Authors

110

  1. YL
    Yusuf Leblebici

    École Polytechnique Fédérale de Lausanne, Switzerland

    3 publications · 52 citations

    3

    h-index

  2. FC
    F. Cannillo

    IMEC, Belgium

    3 publications · 66 citations

    3

    h-index

  3. MA
    Massimo Alioto

    National University of Singapore, Singapore

    3 publications · 52 citations

    3

    h-index

  4. TS
    Tor Sverre Lande

    University of Oslo, Norway

    2 publications · 49 citations

    2

    h-index

  5. JL
    Jean-Didier Legat

    UCLouvain, Belgium

    2 publications · 49 citations

    2

    h-index

1–5 of 110

Venues

  1. IEEE Transactions on Electron Devices

    4 publications · 350 citations

    4

    h-index

  2. 3

    h-index

  3. Electronics Letters

    2 publications · 37 citations

    2

    h-index

  4. 2D Materials

    1 publications · 53 citations

    1

    h-index

  5. IEEE Electron Device Letters

    1 publications · 51 citations

    1

    h-index

1–5