Ultra Low Power Junctionless MOSFETs for Subthreshold Logic Applications

Abstract

In this paper, we report the potential of junctionless (JL) MOS transistors for ultra low power (ULP) subthreshold logic applications. It is demonstrated that double gate (DG) JL devices, which do not require source or drain extension region engineering, can perform significantly better than conventional inversion mode devices, and comparable with underlap DG MOSFETs for ULP applications. Sensitivity analysis shows that among all device parameters, JL devices exhibit least sensitivity to gate length in comparison with inversion mode and underlap MOSFETs. Results highlight the advantages and challenges of JL transistors for next-generation ULP CMOS logic devices.