Standard Delay Format

Standard Delay Format is a standardized textual representation format used in electronic design automation that specifies timing information for integrated circuits by defining delay values and constraints in a structured, tool-interpretable syntax.

7

Publications

360

Citations

33

Authors

16

Institutions

Publications per year

2017–2026

1

Authors

33

  1. ME
    Mark E. Stanton

    University of Delaware, United States

    2 publications · 139 citations

    2

    h-index

  2. KT
    Kun-Han Tsai

    Mentor Technologies, United States

    1 publications · 132 citations

    1

    h-index

  3. DI
    Dragana Ivkovich

    Duke University, United States

    1 publications · 71 citations

    1

    h-index

  4. YS
    Yasuo Satô

    Kyushu Institute of Technology, Japan

    1 publications · 132 citations

    1

    h-index

  5. KC
    Krishnendu Chakrabarty

    Duke University, United States

    1 publications · 30 citations

    1

    h-index

1–5 of 33

Venues

  1. Behavioral Neuroscience

    2 publications · 88 citations

    2

    h-index

  2. 1

    h-index

  3. Proceedings - Asian Test Symposium/Proceedings

    1 publications · 132 citations

    1

    h-index

  4. Microelectronics Journal

    1 publications · 26 citations

    1

    h-index

  5. Developmental Psychobiology

    1 publications · 71 citations

    1

    h-index

1–5