Standard Delay Format
Standard Delay Format is a standardized textual representation format used in electronic design automation that specifies timing information for integrated circuits by defining delay values and constraints in a structured, tool-interpretable syntax.
7
Publications
360
Citations
33
Authors
16
Institutions
Publications per year
2017–2026
1
Parents
7
1–5 of 7
33
2
h-index
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h-index
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1–5 of 33
16
Duke University
Durham, United States
3 h-index
5 publications
308 citations
University of Delaware
Newark, United States
1 h-index
1 publications
68 citations

Yokohama National University
Yokohama, Japan
1 h-index
3 publications
39 citations
Nvidia (United States)
Santa Clara, United States
1 h-index
1 publications
30 citations

Research Triangle Park Foundation
Durham, United States
1 h-index
2 publications
142 citations
Mentor Technologies
Tulsa, United States
1 h-index
7 publications
924 citations

Budapest University of Technology and Economics
Budapest, Hungary
1 h-index
2 publications
52 citations
Indiana University Bloomington
Bloomington, United States
1 h-index
4 publications
80 citations
1–8 of 16
2 publications · 88 citations
2
h-index
1 publications · 30 citations
1
h-index
1 publications · 132 citations
1
h-index
1 publications · 26 citations
1
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1 publications · 71 citations
1
h-index
1–5