Low-latency Interconnects
Low-Latency Interconnects is a type of interconnect architecture designed to minimize communication delay between processing elements by optimizing data transmission speed and reducing routing overhead.
180
Publications
9.3K
Citations
634
Authors
168
Institutions
Publications per year
2017–2026
26
Parents
180
1–5 of 180
634
5
h-index
5
h-index
University of California, Los Angeles, United States
5 publications · 298 citations
5
h-index
4
h-index
4
h-index
1–5 of 634
168
Columbia University
New York, United States
11 h-index
23 publications
930 citations
University of California, Los Angeles
Los Angeles, United States
10 h-index
43 publications
1.7K citations
Georgia Institute of Technology
Atlanta, United States
10 h-index
21 publications
1K citations
Intel (United States)
Santa Clara, United States
6 h-index
12 publications
335 citations
The Ohio State University
Columbus, United States
6 h-index
27 publications
1.1K citations

Keio University
Tokyo, Japan
5 h-index
10 publications
420 citations
IMEC
Leuven, Belgium
5 h-index
17 publications
691 citations
IBM (United States)
Armonk, United States
5 h-index
30 publications
4.7K citations
1–8 of 168
10 publications · 708 citations
10
h-index
7 publications · 291 citations
7
h-index
4 publications · 86 citations
4
h-index
4 publications · 132 citations
4
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3 publications · 488 citations
3
h-index
1–5