High-performance multi-queue buffers for VLSI communications switches

TLDR

Small n × n switches are key components of multistage interconnection networks used in multiprocessors and multicomputers, and their internal buffer design is critical for achieving high throughput and low latency communication. The study aims to evaluate and compare various buffer structures, introducing a new design that supports non‑FIFO message handling and efficient storage allocation for variable‑size packets. The new buffer uses linked‑list based storage managed by a lightweight on‑chip controller, and its performance was assessed by simulation against several alternative designs within a multi‑stage interconnection network. Modeling and simulations show that the new buffer outperforms competing designs, improving performance for systems that currently use less efficient buffers.

Abstract

Small n x n switches are key components of multistage interconnection networks used in multiprocessors as well as in the communication coprocessors used in multicomputers. The design of the internal buffers in these switches is of critical importance for achieving high throughput low latency communication. We discuss several buffer structures and compare them in terms of implementation complexity and their ability to deal with variations in traffic patterns and message lengths. We present a new design of buffers that provide non-FIFO message handling and efficient storage allocation for variable size packets through the use of linked lists managed by a simple on-chip controller. We evaluate the new buffer design by comparing it to several alternative designs in the context of a multi-stage interconnection network. Our modeling and simulations show that the new buffer outperforms its “competition” and can thus be used to improve the performance of a wide variety of systems currently using less efficient buffers.