Æthereal Network on Chip:Concepts, Architectures, and Implementations

TLDR

Semiconductor advances enable more IP blocks per SoC, and interconnects such as buses, switches, and NoCs integrate them, with industry moving toward communication‑centric designs that rely on NoCs. This article introduces the AEthereal NoC. The AEthereal NoC exploits unused capacity by providing best‑effort services alongside guaranteed services.

Abstract

The continuous advances in semiconductor technology enable the integration of increasing numbers of IP blocks in a single SoC. Interconnect infrastructures, such as buses, switches, and networks on chips (NoCs), combine the IPs into a working SoC. Moreover, the industry expects platform-based SoC design to evolve to communication-centric design, with NoCs as a central enabling technology. In this article, we introduce the AEthereal NoC. The tenet of the AEthereal NoC is that guaranteed services (GSs) - such as uncorrupted, lossless, ordered data delivery; guaranteed throughput; and bounded latency - are essential for the efficient construction of robust SoCs. To exploit the NoC capacity unused by the GS traffic, we provide best-effort services.