Hardware Abstraction Layers
Hardware Abstraction Layer is a software interface that belongs to the category of system-level design frameworks, distinguished by its role in encapsulating low-level hardware-specific details to provide uniform and portable access to peripheral devices in embedded systems.
139
Publications
5.8K
Citations
536
Authors
174
Institutions
Publications per year
2017–2026
25
139
The architecture of virtual machines
James E. Smith, Ravi Nair · Computer · 2005 · 570 citations · Full text
1–5 of 139
536
Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France
5 publications · 227 citations
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Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France
4 publications · 132 citations
4
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Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France
3 publications · 123 citations
3
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3
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1–5 of 536
174
Techniques of Informatics and Microelectronics for Integrated Systems Architecture
Grenoble, France
10 h-index
40 publications
1.2K citations
University of California, Berkeley
Berkeley, United States
7 h-index
16 publications
1.4K citations
Stanford University
Stanford, United States
4 h-index
7 publications
259 citations
University of California, Irvine
Irvine, United States
4 h-index
14 publications
559 citations

University of Toronto
Toronto, Canada
3 h-index
9 publications
227 citations
Intel (United States)
Santa Clara, United States
3 h-index
9 publications
362 citations
Massachusetts Institute of Technology
Cambridge, United States
3 h-index
7 publications
240 citations
Hewlett-Packard (United States)
Palo Alto, United States
3 h-index
17 publications
774 citations
1–8 of 174
3 publications · 97 citations
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3 publications · 87 citations
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3 publications · 80 citations
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Conference · 2 publications · 23 citations
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2 publications · 37 citations
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