Dual Threshold Voltage Assignment

Dual Threshold Voltage Assignment is a leakage power reduction method that assigns high-threshold-voltage transistors to non-critical timing paths and low-threshold-voltage transistors to critical paths in order to minimize static power consumption while maintaining circuit performance.

Publications

871

Citations

Authors

Institutions

Publications per year

2017–2026

Variants

Dual-threshold Voltage Assignment

Parents

Leakage Power Reduction

Publications

An efficient algorithm for statistical minimization of total power under timing yield constraints

Murari Mani, Anirudh Devgan, Michael Orshansky · 2005 · 131 citations

Engineering, Computer Engineering, Electrical Engineering +17

Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

P. Pant, Rahul Roy, A. Chattejee · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2001 · 108 citations

Engineering, Computer Engineering, Electrical Engineering +17

Standby power optimization via transistor sizing and dual threshold voltage assignment

Mahesh Ketkar, Sachin S. Sapatnekar · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2002 · 92 citations

Engineering, Computer Engineering, Electrical Engineering +17

A statistical framework for post-silicon tuning through body bias clustering

S. Kulkarni, Dennis Sylvester, David Blaauw · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2006 · 61 citations

Engineering, Computer Engineering, Electrical Engineering +17

Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias

S. Kulkarni, Dennis Sylvester, David Blaauw · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2008 · 44 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 26

Authors

SK
S. Kulkarni
University of Michigan, United States
3 publications · 125 citations
3
h-index
DB
David Blaauw
University of Michigan, United States
3 publications · 125 citations
3
h-index
DS
Dennis Sylvester
University of Michigan, United States
3 publications · 125 citations
3
h-index
AC
Abhijit Chatterjee
Georgia Institute of Technology, United States
3 publications · 59 citations
3
h-index
AS
A.D. Singh
Auburn University, United States
2 publications · 47 citations
2
h-index

1–5 of 55

Institutions

1–8 of 29

Venues

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3 publications · 158 citations
3
h-index
Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design
ICCAD · 3 publications · 173 citations
3
h-index
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
2 publications · 64 citations
2
h-index
Proceedings. 42nd Design Automation Conference, 2005.
Conference · 1 publications · 44 citations
1
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Microsystem Technologies
1 publications · 19 citations
1
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