S. Kulkarni - Concepedia

Author

S. Kulkarni

Also Known As

Guannan Liu, S H Kulkarni, S. Kulkarni, S.H. Kulkarni, Sarvesh H Kulkarni, Sarvesh H. Kulkarni, Sarvesh Kulkarni, Siddharth Kulkarni

Publications

1.3K

Citations

H-Index

Concepts

All Affiliations

University of Michigan Intel (United States)IBM (United States)

About

S. Kulkarni is an author at University of Michigan specializing in engineering, computer architecture, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	14	18	1.2K
2	Computer Engineering	13	17	758
3	Electrical Engineering	13	17	1.1K
4	Applied Physics	3	3	487
5	Computer Science	1	1	60

S. Kulkarni

Publications

1.2K

Citations

H-Index

Page 1

	Year	Citations
Digital circuit applications of resonant tunneling devices Pinaki Mazumder, S. Kulkarni, Mukul Bhattacharya, Proceedings of the IEEE EngineeringBasic Logic GatesSemiconductor DeviceCircuit SystemQuantum Computing	1998	440
Pushing ASIC performance in a power envelope Ruchir Puri, Leon Stok, John Cohn, EngineeringVlsi DesignPower Optimization (Eda)Computer ArchitecturePower Electronics	2003	133
High performance level conversion for dual V/sub DD/ design S. Kulkarni, Dennis Sylvester IEEE Transactions on Very Large Scale Integration (VLSI) Systems Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignVlsi Architecture	2004	98
A 1.1 GHz 12 $\mu$A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, IEEE Journal of Solid-State Circuits Non-volatile MemoryEngineeringVlsi DesignMemory DesignEmerging Memory Technology	2008	71
Architectural Breakdown of End-to-End Latency in a TCP/IP Network Steen Larsen, Parthasarathy Sarangam, Ram Huggahalli, International Journal of Parallel Programming EngineeringUltra-low LatencyComputer EngineeringComputer ArchitectureLow Latency	2009	60
A new algorithm for improved VDD assignment in low power dual VDD systems S. Kulkarni, Ashish N. Srivastava, Dennis Sylvester EngineeringVlsi DesignEnergy EfficiencyPower Optimization (Eda)Computer Architecture	2004	60
A statistical framework for post-silicon tuning through body bias clustering S. Kulkarni, Dennis Sylvester, David Blaauw Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design Hardware SecurityElectrical EngineeringPower-aware ComputingEngineeringVlsi Design	2006	59
Pushing ASIC performance in a power envelope Ruchir Puri, Leon Stok, John R. Cohn, Proceedings of the 40th conference on Design automation - DAC '03 EngineeringVlsi DesignPower Optimization (Eda)Computer ArchitecturePower Electronics	2003	46
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias S. Kulkarni, Dennis Sylvester, David Blaauw IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringVlsi DesignDesign-time OptimizationPower Optimization (Eda)Computer Architecture	2008	44
Fabrication and Electrical Characterization of 3D Vertical Interconnects Michael Newman, Sriram Muthukumar, Mark E. Schuelein, EngineeringComputer ArchitectureInterconnect (Integrated Circuits)Wafer Scale ProcessingDie-stacking Approach	2006	34

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