High performance level conversion for dual V/sub DD/ design

Abstract

Multi-V/sub DD/ design is an effective way to reduce power consumption, but the need for level conversion imposes delay and energy penalties that limit the potential gains. In this paper, we describe new level converting circuits that provide 10%-61% lower energy consumption at equivalent or better speeds compared to those available in the literature. Furthermore, we make the argument that level converters should be evaluated largely by their maximum speed since slower level converters consume valuable timing slack that can be used to reduce the energy of other gates in the circuit. Based on this criterion, we find the new structures to offer up to a 25% speed improvement over conventional level converters. Using an efficient dual V/sub DD/ voltage assignment algorithm, we show that this speed improvement can yield a reduction of up to 7.3% in total circuit power in small benchmark circuits. We also propose embedding the functionality of logic gates into the level converting circuits. For typical values of the second supply voltage, this technique can reduce delay by 15% at constant energy or lower energy by up to 30% at fixed delay.