P. Pant

Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits

P. Pant, Rahul Roy, A. Chattejee · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2001 · 108 citations

Low-power Electronics, Hardware Security, Electrical Engineering +10

On-chip decoupling capacitor optimization using architectural level prediction

Mondira Pant, P. Pant, D.S. Wills · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2002 · 82 citations

Hardware Security, Electrical Engineering, Physical Design (Electronics) +14

An architectural solution for the inductive noise problem due to clock-gating

Mondira Pant, P. Pant, D. Scott Wills et al. · 1999 · 57 citations

Engineering Noise Control, Engineering, Noise Control +18

Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits

P. Pant, Vivek De, Abhijit Chatterjee · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1998 · 55 citations

Low-power Electronics, Hardware Security, Electrical Engineering +14

Understanding Power Supply Droop during At-Speed Scan Testing

P. Pant, Joshua Zelman · 2009 · 55 citations

Electrical Engineering, Engineering, Hardware-in-the-loop Simulation +13