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An architectural solution for the inductive noise problem due to clock-gating
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1999
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Engineering Noise ControlEngineeringNoise ControlEvolvable HardwareComputer ArchitectureComputational ComplexityClock SynchronizationSignal IntegrityElectromagnetic CompatibilityNoise ReductionClock RecoveryTiming AnalysisNoiseInductive Noise ProblemElectrical EngineeringComputer EngineeringArchitectural SolutionComputer ScienceIndustrial NoiseSignal ProcessingClock-gating Share
Article An architectural solution for the inductive noise problem due to clock-gating Share on Authors: Mondira Deb Pant Georgia Institute of Technology, Atlanta, GA Georgia Institute of Technology, Atlanta, GAView Profile , Pankaj Pant View Profile , D. Scott Wills Georgia Institute of Technology, Atlanta, GA Georgia Institute of Technology, Atlanta, GAView Profile , Vivek Tiwari Intel Corporation, Santa Clara, CA Intel Corporation, Santa Clara, CAView Profile Authors Info & Claims ISLPED '99: Proceedings of the 1999 international symposium on Low power electronics and designAugust 1999 Pages 255–257https://doi.org/10.1145/313817.313938Online:17 August 1999Publication History 42citation309DownloadsMetricsTotal Citations42Total Downloads309Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access
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