Mahesh Ketkar

Standby power optimization via transistor sizing and dual threshold voltage assignment

Mahesh Ketkar, Sachin S. Sapatnekar · Digest of technical papers/Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design · 2002 · 92 citations

Engineering, Vlsi Design, Transistor Level +20

A new class of convex functions for delay modeling and its application to the transistor sizing problem [CMOS gates]

Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2000 · 78 citations

Numerical Analysis, Electrical Engineering, Physical Design (Electronics) +13

Gate sizing for cell library-based designs

Shiyan Hu, Mahesh Ketkar, Jiang Hu · Proceedings - ACM IEEE Design Automation Conference · 2007 · 44 citations

Hardware Security, Electrical Engineering, Physical Design (Electronics) +15

Convex delay models for transistor sizing

Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar · 2000 · 34 citations · Full text

Device Modeling, Electrical Engineering, Physical Design (Electronics) +12

Comparative analysis of conventional and statistical design techniques

Steven M. Burns, Mahesh Ketkar, Noel Menezes et al. · Proceedings - ACM IEEE Design Automation Conference · 2007 · 32 citations

Engineering, Vlsi Design, Performance-based Building Design +21