Clock Tree Power Optimization

Clock Tree Power Optimization is a design methodology in low-power digital circuit design that specifically targets the reduction of dynamic and static power consumption in the clock distribution network through strategic sizing, buffering, gating, and routing techniques while maintaining timing integrity and minimizing skew.

132

Publications

4.6K

Citations

326

Authors

104

Institutions

Publications per year

2017–2026

Parents

Low-power Digital Circuit Design

Publications

132

Automated low-power technique exploiting multiple supply voltages applied to a media processor

Kimiyoshi Usami, M. Igarashi, F. Minami et al. · IEEE Journal of Solid-State Circuits · 1998 · 276 citations

Engineering, Computer Engineering, Electrical Engineering +17

Lowering power consumption in clock by using globally asynchronous locally synchronous design style

Ahmed Hemani, T. Meincke, S. Kumar et al. · 1999 · 150 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +16

Reducing power dissipation during test using scan chain disable

Rajkumar Sankaralingam, B. Pouya, Nur A. Touba · 2002 · 150 citations

Engineering, Computer Engineering, Computer Science +17

A gated clock scheme for low power scan testing of logic ICs or embedded cores

Yannick Bonhomme, Patrick Girard, L. Guiller et al. · 2002 · 141 citations

Engineering, Computer Engineering, Electrical Engineering +17

A modified clock scheme for a low power BIST test pattern generator

Patrick Girard, L. Guiller, C. Landrault et al. · 2002 · 134 citations

Engineering, Computer Engineering, Electrical Engineering +17

1–5 of 132

Authors

326

SK
Sung Kyu Lim
Georgia Institute of Technology, United States
10 publications · 294 citations
10
h-index
XZ
Xin Zhao
Georgia Institute of Technology, United States
9 publications · 282 citations
9
h-index
TK
Taewhan Kim
Seoul National University, South Korea
5 publications · 87 citations
5
h-index
DZ
David Z. Pan
The University of Texas at Austin, United States
4 publications · 66 citations
4
h-index
MP
Massoud Pedram
University of Southern California, United States
4 publications · 152 citations
4
h-index

1–5 of 326

Institutions

104

1–8 of 104

Venues

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
12 publications · 478 citations
11
h-index
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
9 publications · 305 citations
9
h-index
International Conference on Computer Aided Design
Conference · 4 publications · 54 citations
4
h-index
ACM Transactions on Design Automation of Electronic Systems
TODAES · 3 publications · 49 citations
3
h-index
Asia and South Pacific Design Automation Conference
Conference · 2 publications · 42 citations
2
h-index

1–5