Clock Domain Design
Clock Domain Design is a hardware architecture methodology in which distinct regions of a digital circuit operate under separately controlled clock signals to enable precise management of timing and power consumption in near-threshold voltage computing environments.
55
Publications
2.2K
Citations
161
Authors
62
Institutions
Publications per year
2017–2026
5
Parents
55
A low-latency FIFO for mixed-clock systems
Tiberiu Chelcea, Steven M. Nowick · 2002 · 87 citations
Engineering, Computer Engineering, Electrical Engineering +15
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Carnegie Mellon University
Pittsburgh, United States
6 h-index
14 publications
326 citations
Princeton University
Princeton, United States
4 h-index
16 publications
1K citations
Technion – Israel Institute of Technology
Haifa, Israel
3 h-index
11 publications
356 citations
University of Bonn
Bonn, Germany
2 h-index
8 publications
317 citations
Philips (Finland)
Vantaa, Finland
2 h-index
2 publications
138 citations
IBM Research - Austin
Austin, United States
2 h-index
2 publications
72 citations
Philips (Netherlands)
Amsterdam, The Netherlands
2 h-index
3 publications
224 citations
Fulcrum Corporation (United States)
Arlington, United States
2 h-index
2 publications
42 citations
1–8 of 62
4 publications · 134 citations
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2 publications · 47 citations
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1 publications · 10 citations
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Conference · 1 publications · 13 citations
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1 publications · 105 citations
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