Clock Domain Design

Clock Domain Design is a hardware architecture methodology in which distinct regions of a digital circuit operate under separately controlled clock signals to enable precise management of timing and power consumption in near-threshold voltage computing environments.

55

Publications

2.2K

Citations

161

Authors

62

Institutions

Publications per year

2017–2026

5

Authors

161

  1. QW
    Qiang Wu

    Northumbria University, United Kingdom

    4 publications · 257 citations

    4

    h-index

  2. MM
    Margaret Martonosi

    Princeton University, United States

    4 publications · 257 citations

    4

    h-index

  3. DW
    Douglas W. Clark

    Princeton University, United States

    4 publications · 257 citations

    4

    h-index

  4. PJ
    Philo Juang

    Princeton University, United States

    4 publications · 257 citations

    4

    h-index

  5. DM
    Diana Marculescu

    Carnegie Mellon University, United States

    4 publications · 89 citations

    4

    h-index

1–5 of 161

Venues

  1. 4

    h-index

  2. IEEE Journal of Solid-State Circuits

    2 publications · 47 citations

    2

    h-index

  3. ACM SIGOPS Operating Systems Review

    1 publications · 10 citations

    1

    h-index

  4. 1

    h-index

  5. IEEE Micro

    1 publications · 105 citations

    1

    h-index

1–5