Resonant tunneling of electrons via 20 nm scale InAs quantum dot and magnetotunneling spectroscopy of its electronic states

M. Narihiro, G. Yusa, Y. Nakamura, +2

Applied Physics Letters

SemiconductorsQuantum ScienceCategoryquantum ElectronicsEngineeringTunneling Microscopy +11

Sub-10-nm planar-bulk-CMOS devices using lateral junction control

Hitoshi Wakabayashi, Shigeharu Yamagami, N. Ikezawa, +7

Device ModelingElectrical EngineeringEngineeringNanoelectronicsSteep Halo +8

Low-power embedded ReRAM technology for IoT applications

M. Ueki, Kazuhiro Takeuchi, Takashi Yamamoto, +15

Sub-50-nm physical gate length CMOS technology and beyond using steep halo

Hitoshi Wakabayashi, M. Ueki, M. Narihiro, +8

IEEE Transactions on Electron Devices

Low-power ElectronicsElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi Design +12

45-nm gate length CMOS technology and beyond using steep halo

Hitoshi Wakabayashi, M. Ueki, M. Narihiro, +8

Low-power ElectronicsElectrical EngineeringEngineeringVlsi DesignNanoelectronics +10

Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

Hitoshi Wakabayashi, T. Ezaki, Toshitsugu Sakamoto, +10

IEEE Transactions on Electron Devices

Device ModelingElectrical EngineeringPhysical Design (Electronics)EngineeringSemiconductor Device +9

Low-power embedded ReRAM technology for IoT applications

M. Ueki, K. T. Akeuchi, Toru Yamamoto, +15

Operation of functional circuit elements using BEOL-transistor with InGaZnO channel for on-chip high/low voltage bridging I/Os and high-current switches

K. Kaneko, H. Sunamura, M. Narihiro, +4

Wide-bandgap SemiconductorEngineeringSemiconductor DeviceSemiconductorsElectronic Devices +17

Feasibility Study of 45-nm-Node Scaled-Down Cu Interconnects With Molecular-Pore-Stacking (MPS) SiOCH Films

Munehiro Tada, Hiroto Ohtake, Fuminori Ito, +9

IEEE Transactions on Electron Devices

Mps Sioch FilmEngineeringFeasibility StudySilicon On InsulatorInterconnect (Integrated Circuits) +17

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Munehiro Tada, T. Tamura, Fuminori Ito, +15

IEEE Transactions on Electron Devices

Materials ScienceDielectric ReliabilityElectrical EngineeringElectromigration TechniqueEngineering +13