On the retention time distribution of dynamic random access memory (DRAM)

T. Hamamoto, S. Sugiura, Seiji Sawada

IEEE Transactions on Electron Devices

Non-volatile MemoryElectrical EngineeringMemory ArchitectureEngineeringNanoelectronics +13

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure

T. Yamagata, M. Mihara, T. Hamamoto, +4

IEEE Journal of Solid-State Circuits

EngineeringMemory DesignVlsi DesignEmerging Memory TechnologyComputer Architecture +16

A 45-ns 16-Mbit DRAM with triple-well structure

Shosuke Fujii, M. Ogihara, Motoki Shimizu, +13

IEEE Journal of Solid-State Circuits

Electrical EngineeringRam PerformanceEngineeringEmerging Memory TechnologyApplied Physics +11

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

N. Shigyo, S. Fukuda, T. Wada, +5

IEEE Transactions on Electron Devices

Device ModelingLow-power ElectronicsElectrical EngineeringThree-dimensional AnalysisEngineering +11

A 667-Mb/s Operating Digital DLL Architecture for 512-Mb DDR SDRAM

T. Hamamoto, K. Furutani, Tetsuo Kubo, +5

IEEE Journal of Solid-State Circuits

Hardware SecurityEngineeringVlsi DesignType SdramsHierarchical Phase +10

FBC (Floating Body Cell) for embedded DRAM on SOI

K. Inoh, T. Shino, Hisao Yamada, +11

Hardware SecurityNon-volatile MemoryElectrical EngineeringCell TransistorEngineering +9

Well concentration: a novel scaling limitation factor derived from DRAM retention time and its modeling

T. Hamamoto, S. Sugiura, Seiji Sawada

Electrical EngineeringMemory ArchitectureEngineeringDram Retention TimePhysics +13

A 45 ns 16 Mb DRAM with triple-well structure

S. Fujii, M. Ogihara, Motoki Shimizu, +13

Ns 16EngineeringMemory DesignEmerging Memory TechnologyComputer Architecture +16

Highly scalable FBC (Floating Body Cell) with 25nm BOX structure for embedded DRAM applications

T. Shino, Isao Higashi, Koji Fujita, +8

Non-volatile MemoryEngineeringEmerging Memory TechnologyEmbedded Dram ApplicationsComputer Architecture +14

Fully-depleted FBC (floating body cell) with enlarged signal window and excellent logic process compatibility

T. Shino, Tatsuya Higashi, N. Kusunoki, +11

Non-volatile MemoryElectrical EngineeringEngineeringVlsi DesignStandard Salicide Process +12