T. Hamamoto

On the retention time distribution of dynamic random access memory (DRAM)

T. Hamamoto, S. Sugiura, Seiji Sawada · IEEE Transactions on Electron Devices · 1998 · 246 citations

Non-volatile Memory, Electrical Engineering, Memory Architecture +15

A 288-kb fully parallel content addressable memory using a stacked-capacitor cell structure

T. Yamagata, M. Mihara, T. Hamamoto et al. · IEEE Journal of Solid-State Circuits · 1992 · 50 citations

Engineering, Memory Design, Vlsi Design +18

A 45-ns 16-Mbit DRAM with triple-well structure

Shosuke Fujii, M. Ogihara, Motoki Shimizu et al. · IEEE Journal of Solid-State Circuits · 1989 · 43 citations

Electrical Engineering, Ram Performance, Engineering +13

Three-dimensional analysis of subthreshold swing and transconductance for fully-recessed-oxide (trench) isolated 1/4- mu m-width MOSFETs

N. Shigyo, S. Fukuda, T. Wada et al. · IEEE Transactions on Electron Devices · 1988 · 41 citations

Device Modeling, Low-power Electronics, Electrical Engineering +13

A 667-Mb/s Operating Digital DLL Architecture for 512-Mb DDR SDRAM

T. Hamamoto, K. Furutani, Tetsuo Kubo et al. · IEEE Journal of Solid-State Circuits · 2004 · 36 citations

Hardware Security, Engineering, Vlsi Design +12