Byron Ho - Concepedia

Author

Byron Ho

University of California, Berkeley

Also Known As

B C Ho, B. Ho, Byron Ho

Publications

596

Citations

H-Index

Concepts

All Affiliations

University of California, Berkeley Soitec (France)Synopsys (Switzerland)CEA Grenoble Synopsys (United States)

About

Byron Ho is an author at University of California, Berkeley specializing in microelectronics, electrical engineering, and engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	7	7	517
2	Applied Physics	6	6	473
3	Medicine	1	1	29
4	Natural Sciences	1	1	29
5	Biochemistry	1	1	29

Byron Ho

Publications

557

Citations

H-Index

Page 1

	Year	Citations
A 10nm high performance and low-power CMOS technology featuring 3<sup>rd</sup> generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects C. Auth, A. Aliyarukunju, M. Asoro, EngineeringIntegrated CircuitsHigh PerformanceInterconnect (Integrated Circuits)High-speed Electronics	2017	353
Effectiveness of Stressors in Aggressively Scaled FinFETs Nuo Xu, Byron Ho, Munkang Choi, IEEE Transactions on Electron Devices Stress Transfer EfficiencySemiconductor TechnologyElectrical EngineeringEngineeringTechnology Scaling	2012	44
Design Optimization of Multigate Bulk MOSFETs Byron Ho, Xin Sun, Changhwan Shin, IEEE Transactions on Electron Devices Electrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignDevice Design Parameters	2012	33
Dipalmitoylphosphatidylcholine in amniotic fluid quantified by fast-atom-bombardment mass spectrometry. Byron Ho, Catherine Fenselau, G.E. Hansen, Clinical Chemistry Amniotic FluidBiochemistryAnalytical InstrumentationNatural SciencesGas Chromatography	1983	29
Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs Nuo Xu, Byron Ho, F. Andrieu, IEEE Electron Device Letters Device ModelingFuture Technology NodesElectrical EngineeringEngineeringTechnology Scaling	2012	27
Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs Nuo Xu, F. Andrieu, Byron Ho, Electrical EngineeringEngineeringUltra-thin BodyCarrier Transport BehaviorNanoelectronics	2012	23
Planar GeOI TFET Performance Improvement With Back Biasing Peter Matheu, Byron Ho, Zachery A. Jacobson, IEEE Transactions on Electron Devices Categoryquantum ElectronicsEngineeringSemiconductor DeviceElectromagnetic CompatibilityElectronic Engineering	2012	19
A versatile 0.13 μm CMOS platform technology supporting high performance and low power applications A.H. Perera, B. Smith, N. Cave, Low Power ApplicationsEngineeringVlsi DesignNm Krf LithographyDevice Integration	2002	18
Evolutionary MOSFET Structure and Channel Design for Nanoscale CMOS Technology Byron Ho eScholarship (California Digital Library)	2012	11

Page 1