Sujith Subramanian

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Anshul Gupta, Olalla Varela Pedreira, Goutham Arutchelvan et al. · IEEE Transactions on Electron Devices · 2020 · 38 citations

Engineering, Electrical Engineering, Materials Science +17

CFET SRAM With Double-Sided Interconnect Design and DTCO Benchmark

Hsiao-Hsuan Liu, P. Schuddinck, Zhenlin Pei et al. · IEEE Transactions on Electron Devices · 2023 · 32 citations

Engineering, Computer Engineering, Electrical Engineering +17

First monolithic integration of Ge P-FETs and InAs N-FETs on silicon substrate: Sub-120 nm III-V buffer, sub-5 nm ultra-thin body, common raised S/D, and gate stack modules

Sachin Yadav, Kian-Hua Tan, Annie et al. · 2015 · 15 citations

Engineering, Electrical Engineering, Materials Science +17

CoInGaAs as a novel self-aligned metallic source/drain material for implant-less In0.53Ga0.47As n-MOSFETs

Ivana Ivana, Eugene Y.-J. Kong, Sujith Subramanian et al. · Solid-State Electronics · 2012 · 13 citations

Engineering, Electrical Engineering, Materials Science +13

Selective Wet Etching Process for Ni-InGaAs Contact Formation in InGaAs N-MOSFETs with Self-Aligned Source and Drain

Sujith Subramanian, Ivana Ivana, Qian Zhou et al. · Journal of The Electrochemical Society · 2011 · 12 citations

Engineering, Electrical Engineering, Materials Science +17