Keat Mun Hoe - Concepedia

Author

Keat Mun Hoe

Institute of Microelectronics

Also Known As

K. Hoe, K. M. Hoe, K.M. Hoe, Keat Mun Hoe, Keat-Mun Hoe

Publications

429

Citations

H-Index

Concepts

All Affiliations

Institute of Microelectronics National University of Singapore Singapore Science Park Institute of Materials Research and Engineering Data Storage Institute

About

Keat Mun Hoe is an author at Institute of Microelectronics specializing in electrical engineering, engineering, and applied physics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	10	10	397
2	Electrical Engineering	10	10	397
3	Applied Physics	9	9	367
4	Materials Science	3	3	80
5	Materials Engineering	1	1	17

Keat Mun Hoe

Publications

397

Citations

H-Index

Page 1

	Year	Citations
Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance Navab Singh, F. Y. Lim, Weiwei Fang, EngineeringSilicon On InsulatorSemiconductor DeviceLow TemperatureSemiconductors	2006	156
Nickel-Silicide:Carbon Contact Technology for N-Channel MOSFETs With Silicon–Carbon Source/Drain Rinus T. P. Lee, Litao Yang, Tsung-Yang Liow, IEEE Electron Device Letters Materials ScienceSemiconductor TechnologyElectrical EngineeringCarbon Contact TechnologyContact Technology	2008	46
Three Dimensionally Stacked SiGe Nanowire Array and Gate-All-Around p-MOSFETs L. K. Bera, Hai Son Nguyen, Navaneet Kumar Singh, Electrical EngineeringSi-cmos Compatible ProcessEngineeringNanoelectronicsNanotechnology	2006	44
Ge-Rich (70%) SiGe Nanowire MOSFET Fabricated Using Pattern-Dependent Ge-Condensation Technique Yu Jiang, Navab Singh, T. Y. Liow, IEEE Electron Device Letters Device ModelingSige Nanowire MosfetElectrical EngineeringSemiconductor TechnologyEngineering	2008	31
Strained p-Channel FinFETs With Extended $\Pi$-Shaped Silicon–Germanium Source and Drain Stressors Kian-Ming Tan, Tsung-Yang Liow, Rinus T. P. Lee, IEEE Electron Device Letters P-channel FinfetsSemiconductor TechnologyElectrical EngineeringSilicon–germanium SourceEngineering	2007	30
Demonstration of Schottky Barrier NMOS Transistors With Erbium Silicided Source/Drain and Silicon Nanowire Channel Eu Jin Tan, K. L. Pey, Navab Singh, IEEE Electron Device Letters Erbium Silicided Source/drainSemiconductor TechnologyElectrical EngineeringSub XmlnsErbium Disilicide	2008	27
SiGeO layer formation mechanism at the SiGe/oxide interfaces during Ge condensation S. Balakumar, Peng Suo, Keat Mun Hoe, Applied Physics Letters EngineeringSige/oxide InterfacesIntegrated CircuitsSilicon On InsulatorGe Condensation Technique	2007	22
A High-Stress Liner Comprising Diamond-Like Carbon (DLC) for Strained p-Channel MOSFET Kian-Ming Tan, Ming Zhu, Weiwei Fang, IEEE Electron Device Letters Materials EngineeringDiamond-like CarbonElectrical EngineeringEngineeringNanoelectronics	2008	17
Fabrication of thick SiGe on insulator (Si0.2Ge0.8OI) by condensation of SiGe∕Si superlattice grown on silicon on insulator S. Balakumar, Shu Ling Peng, Keat Mun Hoe, Applied Physics Letters Materials ScienceElectrical EngineeringSige∕si Superlattice GrownSgoi FilmThick Sige	2007	12
A New Liner Stressor with Very High Intrinsic Stress (&#x226B; 6 GPa) and Low Permittivity Comprising Diamond-Like Carbon (DLC) for Strained P-Channel Transistors Kian-Ming Tan, Ming Zhu, Weiwei Fang, EngineeringIntegrated CircuitsInterconnect (Integrated Circuits)Semiconductor DeviceNew Liner Stressor	2007	12

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