Jeng-Jie Peng

ESD test methods on integrated circuits: an overview

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang · 2002 · 46 citations

Engineering, Electrical Engineering, Microelectronics +10

Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs

Ming-Dou Ker, Jeng-Jie Peng · IEEE Transactions on Components and Packaging Technologies · 2002 · 20 citations

Engineering, Computer Engineering, Electrical Engineering +17

Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution [CMOS]

Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang · 2003 · 14 citations

Engineering, Electrical Engineering, Hardware Security +8

Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits

Jeng-Jie Peng, Ming‐Dou Ker, Hsin-Chin Jiang · 2003 · 13 citations

Engineering, Computer Engineering, Electrical Engineering +10

Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology

Ming‐Dou Ker, Jeng-Jie Peng · 2002 · 10 citations

Engineering, Electrical Engineering, Microelectronics +15