ESD test methods on integrated circuits: an overview

Abstract

ESD phenomenon has become a serious problem for IC products fabricated by deep-submicron CMOS technologies. To qualify the ESD immunity of IC products, there are some test methods and standards developed by certain organizations, such as ESDA, AEC, EIA/JEDEC, and MIL-STD organizations. ESD events have been classified into 4 models, which are HBM, MM, CDM, and SDM. There are 4 modes of pin combinations for ESD zapping on the IC pins, which are specified as (1) pin-to-VSS, (2) pin-to-VDD, (3) pin-to-pin, and (4) VDD-to-VSS. All the test methods are designed to evaluate the ESD immunity of IC products. The zap number, zap interval, and sample size are all well defined in the related industrial standards. This paper provides an overview among ESD test methods on IC products. In general, the commercial IC products are requested to sustain at least 2-kV HBM, 200-V MM, and 1-kV CDM ESD stresses.