J. Y. Wu

CMP process development for the via-middle 3D TSV applications at 28nm technology node

T.C. Tsai, W. C. Tsao, Welch Lin et al. · Microelectronic Engineering · 2011 · 55 citations

Engineering, Computer Engineering, Electrical Engineering +11

Process development of high-k metal gate aluminum CMP at 28nm technology node

Yeh-Hsin Hsien, H. K. Hsu, T.C. Tsai et al. · Microelectronic Engineering · 2011 · 35 citations

Engineering, Electrical Engineering, Materials Science +16

Embedded memory and ARM Cortex-M0 core using 60-nm C-axis aligned crystalline indium-gallium-zinc oxide FET integrated with 65-nm Si CMOS

Tatsuya Onuki, Wataru Uesugi, Hikaru Tamura et al. · 2016 · 30 citations

Engineering, Computer Engineering, Electrical Engineering +16

Ultra low p-type SiGe contact resistance FinFETs with Ti silicide liner using cryogenic contact implantation amorphization and Solid-Phase Epitaxial Regrowth (SPER)

Yu‐Chi Yang, N. Breil, C. Y. Yang et al. · 2016 · 26 citations

Engineering, Electrical Engineering, Materials Science +13

A 140 MHz 1 Mbit 2T1C gain-cell memory with 60-nm indium-gallium-zinc oxide transistor embedded into 65-nm CMOS logic process technology

Takahiko Ishizu, Shuhei Nagatsuka, Momoyo Yamaguchi et al. · 2017 · 24 citations

Engineering, Computer Engineering, Electrical Engineering +17