Hsiao Hsiang-Yao

Stress Analysis and Design Optimization for Low-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> Chip With Cu Pillar Interconnection

Fa Xing, Jong‐Kai Lin, K. Y. Au et al. · IEEE Transactions on Components Packaging and Manufacturing Technology · 2015 · 23 citations

Numerical Analysis, Engineering, Cu Pillar +18

Ultra-Thin FO Package-on-Package for Mobile Application

Hsiao Hsiang-Yao, Soon Wee Ho, Simon Siak Boon Lim et al. · 2019 · 18 citations

Engineering, Computer Architecture, Bottom Package +19

Double Mold Antenna in Package for 77 GHz Automotive Radar

Soon Wee Ho, Soh Siew Boon, Lau Boon Long et al. · 2020 · 15 citations

High Density RDL build-up on FO-WLP using RDL-first Approach

Soon Wee Ho, Hsiao Hsiang-Yao, Simon Siak Boon Lim et al. · 2019 · 13 citations

Materials Science, Electrical Engineering, Engineering +14

Thermal Compression Bonding of 30um Pitch Cu Pillar Microbump on Organic Substrate with Bare Cu Bondpad

K. Y. Au, Jong‐Kai Lin, Hsiao Hsiang-Yao et al. · 2016 · 12 citations

Engineering, Cu Pillar, Mechanical Engineering +18