Y. Taur

CMOS scaling into the 21st century: 0.1 µm and beyond

Y. Taur, Y. J. Mii, D.J. Frank et al. · IBM Journal of Research and Development · 1995 · 113 citations

Engineering, Computer Engineering, Electrical Engineering +17

High performance 0.1 μm CMOS devices with 1.5 V power supply

Y. Taur, Shalom J. Wind, Y. J. Mii et al. · 2002 · 92 citations

Engineering, Computer Engineering, Electrical Engineering +17

A variable-stress shallow trench isolation (STL) technology with diffused sidewall doping for submicron CMOS

B. Davari, Charles W. Koburger, T. Furukawa et al. · 2003 · 57 citations

Engineering, Computer Engineering, Electrical Engineering +17

A new planarization technique, using a combination of RIE and chemical mechanical polish (CMP)

B. Davarik, Charles W. Koburger, R. Schulz et al. · 2003 · 55 citations

Engineering, Electrical Engineering, Materials Science +17

Doping of n/sup +/ and p/sup +/ polysilicon in a dual-gate CMOS process

C. Y. Wong, J.Y.-C. Sun, Y. Taur et al. · 2003 · 37 citations

Engineering, Electrical Engineering, Microelectronics +16