Chuanchuan Hou

High performance 22/20nm FinFET CMOS devices with advanced high-K/metal gate scheme

Chau-Neng Wu, Dongyang Lin, A. Keshavarzi et al. · 2010 · 105 citations

Finfet Cmos Devices, Electrical Engineering, Engineering +12

A 0.13 μm CMOS technology with 193 nm lithography and Cu/low-k for high performance applications

K.K. Young, S.Y. Wu, Chung-Cheng Wu et al. · 2002 · 50 citations

Engineering, Vlsi Design, Computer Architecture +18

Complementary Field-Effect Transistor (CFET) Demonstration at 48nm Gate Pitch for Future Logic Technology Scaling

Siyong Liao, T.K. Chiu, Wei-Xiang You et al. · 2023 · 47 citations

Complementary Field-effect Transistor, Electrical Engineering, Engineering +12

A 0.18 μm CMOS logic technology with dual gate oxide and low-k interconnect for high-performance and low-power applications

C.H. Diaz, K.L. Young, Johnny Hsu et al. · 2003 · 36 citations

Low-power Electronics, Electrical Engineering, μM Cmos +13

Impedance Modelling Mechanisms and Stability Issues of Single Phase Inverter With SISO Structure and Frequency Coupling Effect

Zhengzhao Li, Miao Zhu, Chuanchuan Hou et al. · IEEE Transactions on Energy Conversion · 2021 · 29 citations

Electrical Engineering, Mirror Frequency Effect, Impedance Model +11