Zhixian Chen

Vertical Si-Nanowire <formula formulatype="inline"><tex Notation="TeX">$n$</tex></formula>-Type Tunneling FETs With Low Subthreshold Swing (<formula formulatype="inline"><tex Notation="TeX">$\leq \hbox{50}\ \hbox{mV/decade}$</tex> </formula>) at Room Temperature

Ramanathan Gandhi, Zhixian Chen, Navab Singh et al. · IEEE Electron Device Letters · 2011 · 329 citations

Engineering, Integrated Circuits, Semiconductor Device +18

CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing

Ramanathan Gandhi, Zhixian Chen, Navab Singh et al. · IEEE Electron Device Letters · 2011 · 188 citations

Engineering, Fabricated P-tfet Devices, Integrated Circuits +17

Multifunctional MoTe₂ Fe‐FET Enabled by Ferroelectric Polarization‐Assisted Charge Trapping

Jing Gao, Xu Lian, Zhixian Chen et al. · Advanced Functional Materials · 2022 · 76 citations

Engineering, Emerging Memory Technology, Optoelectronic Devices +18

The Role of Ti Capping Layer in HfO<sub><italic>x</italic></sub>-Based RRAM Devices

Zheng Fang, Xinpeng Wang, Joon Sohn et al. · IEEE Electron Device Letters · 2014 · 72 citations

Ti Capping Layer, Thin Ti Layer, Electrical Engineering +15

New degradation mechanisms and reliability performance in tunneling field effect transistors

G. F. Jiao, Zhixian Chen, H.Y. Yu et al. · 2009 · 61 citations

Engineering, Hc Degradation, Semiconductor Device +19