Pavan Kumar Hanumolu

Analysis of charge-pump phase-locked loops

Pavan Kumar Hanumolu, Merrick Brownlee, Kartikeya Mayaram et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2004 · 167 citations

Engineering, Electrical Engineering, Systems Engineering +17

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

V. Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moon et al. · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2007 · 147 citations

Engineering, Electrical Engineering, Analog Electronics +4

A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC

Ahmed Elkholy, Tejasvi Anand, Woo‐Seok Choi et al. · IEEE Journal of Solid-State Circuits · 2015 · 130 citations

Engineering, Electrical Engineering, Analog Electronics +16

A Digital PLL With a Stochastic Time-to-Digital Converter

V. Kratyuk, Pavan Kumar Hanumolu, Kerem Ok et al. · IEEE Transactions on Circuits and Systems I Regular Papers · 2008 · 107 citations

Engineering, Electrical Engineering, Analog Electronics +16

Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

Amr Elshazly, Rajesh Inti, Ben Young et al. · IEEE Journal of Solid-State Circuits · 2013 · 90 citations

Engineering, Computer Engineering, Electrical Engineering +17