Jouke Verbree

A structured and scalable test access architecture for TSV-based 3D stacked ICs

Erik Jan Marinissen, Jouke Verbree, Mario Konijnenburg · 2010 · 147 citations

Engineering, Probe Pads, Dft Architecture +18

3D DfT architecture for pre-bond and post-bond testing

Erik Jan Marinissen, Chun‐Chuan Chi, Jouke Verbree et al. · 2010 · 65 citations

Engineering, 3D-sic Test Flow, Dft Architecture +22

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs

Brandon Noia, Krishnendu Chakrabarty, S.K. Goel et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 2011 · 63 citations

3D Ic Architecture, Test Scheduling, Vlsi Design +15

Test-architecture optimization for TSV-based 3D stacked ICs

Brandon Noia, Sandeep Goel, Krishnendu Chakrabarty et al. · 2010 · 60 citations

3D Ic Architecture, Physical Design (Electronics), Engineering +13

On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking

Jouke Verbree, Erik Jan Marinissen, Philippe Roussel et al. · 2010 · 52 citations

Engineering, Computer Architecture, Physical Design (Electronics) +18