C. Sheraw - Concepedia

Concepedia

Author

C. Sheraw

Pennsylvania State University

Also Known As

C. D. Sheraw, C. Sheraw, C.D. Sheraw, Chris D Sheraw, Chris D. Sheraw, Chris Sheraw

31

Publications

2.4K

Citations

16

H-Index

45

Concepts

All Affiliations

Pennsylvania State University IBM (United States)IBM Research - Thomas J. Watson Research Center Advanced Micro Devices (United States)Advanced Micro Devices (Canada)

CS

About

C. Sheraw is an author at Pennsylvania State University specializing in engineering, electrical engineering, and applied physics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	15	16	2.2K
2	Applied Physics	12	13	1.4K
3	Chemistry	5	5	667
4	Computer Engineering	5	5	328
5	Chemical Engineering	1	1	35

C. Sheraw

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18

Publications

2.4K

Citations

16

H-Index

	Year	Citations
Organic thin-film transistor-driven polymer-dispersed liquid crystal displays on flexible polymeric substrates C. Sheraw, Lipu Zhou, J.R. Huang, Applied Physics Letters Materials ScienceSmall DisplaysEngineeringElectronic MaterialsFlexible Electronics	2002	771
Functionalized Pentacene Active Layer Organic Thin‐Film Transistors C. Sheraw, Thomas N. Jackson, David L. Eaton, Advanced Materials Pentacene MoleculesElectronic DevicesEngineeringElectronic MaterialsOrganic Electronics	2003	407
Contact resistance in organic thin film transistors Hagen Klauk, Günter Schmid, Wolfgang Radlik, Solid-State Electronics Electrical EngineeringEngineeringOrganic ElectronicsApplied PhysicsOrganic Semiconductor	2002	351
Analog and digital circuits using organic thin-film transistors on polyester substrates M. Kane, J. Campi, ML Hammond, IEEE Electron Device Letters EngineeringOrganic ElectronicsPolyester SubstratesAnalog DesignChemistry	2000	184
High performance 14nm SOI FinFET CMOS technology with 0.0174&#x00B5;m<sup>2</sup> embedded DRAM and 15 levels of Cu metallization C-H. Lin, B. Greene, J. Cai,	2014	128
High Performance 45-nm SOI Technology with Enhanced Strain, Porous Low-k BEOL, and Immersion Lithography P. Agnello, T. Ivers, C. Warm, EngineeringVlsi DesignEnhanced StrainPorous Low-k BeolIntegrated Circuits	2006	115
22nm High-performance SOI technology featuring dual-embedded stressors, Epi-Plate High-K deep-trench embedded DRAM and self-aligned Via 15LM BEOL P. Chang, C. Ortolland, David Fried, High-performance Soi TechnologyEngineeringVlsi DesignComputer ArchitectureInterconnect (Integrated Circuits)	2012	89
A 7nm CMOS technology platform for mobile and high performance compute application B. Jagannathan, Akihisa Ogino, D. Jaeger, EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsHardware Systems	2017	58
Challenges and Opportunities for High Performance 32 nm CMOS Technology J.W. Sleight, Isaac Lauer, O. Dokumaci, EngineeringVlsi DesignRelaxed Pitch DesignsComputer ArchitectureInterconnect (Integrated Circuits)	2006	48
Spin-on Polymer Gate Dielectric for High Performance Organic Thin Film Transistors C. Sheraw, David J. Gundlach, Thomas N. Jackson MRS Proceedings Materials ScienceConducting PolymerElectrical EngineeringEngineeringSemiconducting Polymer	1999	37

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