Ji-Hoon Lim

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Seung-Jun Bae, Kwang‐Il Park, Jeong-Don Ihm et al. · IEEE Journal of Solid-State Circuits · 2008 · 65 citations

Mb Gddr4, Engineering, Vlsi Design +17

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Tae-Young Oh, Young‐Soo Sohn, Seung-Jun Bae et al. · IEEE Journal of Solid-State Circuits · 2010 · 34 citations

Engineering, Memory Design, Vlsi Design +16

Effects of Organic or Inorganic Acid Supplementation on Growth Performance, Nutrient Digestibility and White Blood Cell Counts in Weanling Pigs

Dong Yong Kil, L. G. Piao, Hua Long et al. · Asian-Australasian Journal of Animal Sciences · 2005 · 33 citations · Full text

A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%–80% Input Duty Cycle for SDRAMs

Ji-Hoon Lim, Jun-Hyun Bae, Jaemin Jang et al. · IEEE Transactions on Circuits & Systems II Express Briefs · 2015 · 29 citations

Electrical Engineering, Dcc Output, Engineering +11

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

Soo-Min Lee, Ji-Hoon Lim, Il-Min Yi et al. · IEEE Journal of Solid-State Circuits · 2016 · 15 citations

Transceiver Chip, Engineering, Mixed-signal Integrated Circuit +6