Saravanan Rajamani

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 532 citations

Engineering, Computer Engineering, Electrical Engineering +16

A 10nm high performance and low-power CMOS technology featuring 3^rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects

C. Auth, A. Aliyarukunju, M. Asoro et al. · 2017 · 369 citations

Engineering, Computer Engineering, Electrical Engineering +17

Improved Sensitivity with Low Limit of Detection of a Hydrogen Gas Sensor Based on rGO-Loaded Ni-Doped ZnO Nanostructures

Vijendra Singh Bhati, Sapana Ranwa, Saravanan Rajamani et al. · ACS Applied Materials & Interfaces · 2018 · 183 citations

Engineering, Materials Engineering, Materials Science +17

Effect of self-heating on electrical characteristics of AlGaN/ GaN HEMT on Si (111) substrate

Adarsh Nigam, Thirumaleshwara N. Bhat, Saravanan Rajamani et al. · AIP Advances · 2017 · 84 citations · Full text

Engineering, Electrical Engineering, Materials Science +17

Low-k interconnect stack with multi-layer air gap and tri-metal-insulator-metal capacitors for 14nm high volume manufacturing

K. Fischer, M. Agostinelli, C. Allen et al. · 2015 · 68 citations

Engineering, Computer Engineering, Electrical Engineering +14