S. Chouksey

A 14nm logic technology featuring 2<sup>nd</sup>-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm<sup>2</sup> SRAM cell size

S. Natarajan, M. Agostinelli, Sheikh A. Akbar et al. · 2014 · 521 citations

-Generation Finfet, Rectangular Fins, Engineering +16

3D heterogeneous integration of high performance high-K metal gate GaN NMOS and Si PMOS transistors on 300mm high-resistivity Si substrate for energy-efficient and compact power delivery, RF (5G and beyond) and SoC applications

Han Wui Then, Changyang Huang, B. Krist et al. · 2019 · 99 citations

Gate-All-Around Strained Si_0.4Ge_0.6 Nanosheet PMOS on Strain Relaxed Buffer for High Performance Low Power Logic Application

Ankur Agrawal, S. Chouksey, W. Rachmady et al. · 2020 · 46 citations

Semiconductors, Semiconductor Technology, Electrical Engineering +12

GaN and Si Transistors on 300mm Si(111) Enabled by 3D Monolithic Heterogeneous Integration

Han Wui Then, M. Radosavljević, P. Agababov et al. · 2020 · 24 citations

Monolithic Heterogeneous Integration, Semiconductor Technology, Electrical Engineering +15

Insights on Design and Scalability of Thin-BOX FD/SOI CMOS

S. Chouksey, J.G. Fossum, Shishir Agrawal · IEEE Transactions on Electron Devices · 2010 · 16 citations

Low-power Electronics, Electrical Engineering, Thin-box Fd/soi Cmos +13